1. Field of the Invention
The present invention relates to a circuit that provides a transition between sub-circuit components operating at different high-potential levels. In particular, the present invention relates to a dual-potential-interface-buffer circuit that operates independent of the sequencing of the respective high-potential power rails without significant power losses in the system. More particularly, the present invention is directed to an interface buffer circuit that provides an interface between subcircuits supplied by a 3 V high-potential rail and subcircuits supplied by a 5 V high-potential rail while preventing any direct static current leakage path from either high-potential rail to the other or to ground.
2. Description of the Prior Art
It is well known that continuing goals in the electronics industry are to: 1) increase the speed of; 2) reduce the size of; and 3) reduce the power required for electronic systems including, but not limited to, computer systems. Applications directly related to achieving these goals include laptop computers, handheld computers, and the like. It is well known that in order to accomplish these goals the size of primary components--mainly MOS and bipolar transistors and related elements--must be reduced. This reduction in component size has been achieved--and continues to be improved--through improved fabrication techniques. The smaller semiconductor devices created are faster and require less power to operate than their predecessors. As a result of these efforts, recent industry guidelines have been implemented for standardization of the power supply utilized to operate these components. In particular, the Joint Electron Device Engineering Council (JEDEC) of the Electronic Industries Association has adopted a standard for new "low" high-potential power rails-- JEDEC Standard 8-1A. Standard 8-1A provides for the implementation of high-potential rails at a nominal value of 3.3 V--generally referred to as a 3 V supply.
The use of a 3 V power supply is advantageous in that there is less power dissipation and so the operating life of the system is extended-in comparison to circuitry powered by a standard 5 V supply. It is also useful to incorporate MOS transistors that can operate on the 3 V power supply because their logic-high potential levels are then comparable to the logic-high potential levels for bipolar transistors.
While utilization of semiconductor devices that only require the 3 V supply to operate is a primary goal, many systems and subsystems in use today are fabricated of "large" components that must be powered by the more conventional 5 V supply. As a result, subcircuits having the new smaller devices are often coupled to circuitry that operates on a 5 V supply. One particular example of a joining of subcircuits using unequal power supplies is the personal digital assistant--a term commonly used to describe very small personal computers such as handheld computers. These systems incorporate microprocessors, peripheral ports, and the like that operate on a 3 V supply. However, most disk controllers to which these subsystems are coupled operate on a 5 V supply. Because of the obvious need to transfer data between these subsystems, power supply "translators" are necessary to provide for appropriate transitions between the subcircuits operating on incompatible power supplies.
Of key importance in the design of these 3 V,5 V translators is the ability to prevent unwanted conduction through the circuit--a problem of particular concern in the field of translators, given the fact that coupled subsystems are operating with unequal high-potential levels and logic-high levels. In most cases, CMOS devices operating at full 5 V rail-to-rail logic levels have no direct current path between the high-potential rail, generally designated as V.sub.CC, and the low-potential rail GND and so there is no unwanted conduction path between the two rails. However, when circuit devices operate at logic levels generally associated with bipolar transistors--that is, with logic-high levels on the order of 3.5 V on a 5 V high-potential power rail--such conduction paths can exist. Of course, similar logic-high levels are anticipated, as noted, in MOS devices operating on a 3 V power supply. As a result, when MOS transistors operating on unequal power supplies are coupled, the same unwanted conduction paths observed in BiCMOS circuits arise.
Static current, or leakage current, or static high current, designated generally as I.sub.CCt, are terms used to define the condition when there is a continuous conduction path from or to V.sub.CC when none should exist. This static current acts to dissipate power in a subsystem where power usage is not desired. While I.sub.CCt is often quite small on an isolated basis, in a system having many subcircuits manifesting this leakage current, the power dissipation multiplies to the point where it can significantly reduce the power available for desired operations. This is particularly critical where the initial power supply voltage is reduced, such as is the case with 3 V high-potential rails. Therefore, 3 V,5 V translator designs must be focused on the importance of minimizing, if not eliminating, unwanted static current.
Examples of translators presently available are illustrated in FIGS. 1 and 2. The translator illustrated in FIG. 1 includes an input inverter stage PA1,NA1 coupled to a first high-potential rail V.sub.CCA and pullup/pulldown output stage PB1, NB1 coupled to a second high-potential rail V.sub.CCB, where the potentials of V.sub.CCA and V.sub.CCB are not equal. Optionally, an NMOS swing transistor NA3, with its drain tied to its control node so that it is always on, can be coupled between V.sub.CCA and PMOS transistor PA1 so as to reduce the voltage at the source of PA1. In this way, V.sub.IN can turn PA1 on or off faster. The circuit illustrated in FIG. 1 provides translation without static current I.sub.CCt when V.sub.IN is logic-high, whether that logic-high is at a potential of 5 V or 3 V. This circuit also provides translation without static current I.sub.CCt when V.sub.IN is logic-low, but only when V.sub.CCA &gt;V.sub.CCB. When V.sub.CCB &gt;V.sub.CCA and V.sub.IN is logic-low, I.sub.CCt does not equal zero because the potential at the gate of pullup PMOS transistor PB1 is insufficient to turn that transistor off. Therefore, the FIG. 1 translator fails to prevent static current in all cases.
The translator illustrated in FIG. 2 includes the input inverter stage PA1, NA1, and a pullup/pulldown stage PB2,NB2, similar to that of the FIG. 1 translator, as part of an output stage coupled primarily to high-potential rail V.sub.CCB. It is necessary to include a blocking diode D1 in the FIG. 2 translator in order to block conduction from V.sub.CCB through PMOS transistor PB1 to V.sub.CCA when V.sub.CCB &gt;V.sub.CCA and V.sub.IN is logic-high. Additionally, latch transistors PB1 and NB1 pull node A either all the way up to the potential of high-potential rail V.sub.CCB or all the way down to the potential of low-potential rail GND so that the gates of pullup and pulldown transistors PB2 and NB2 are at one or the other of those levels. In that way, PMOS transistor PB2 and NMOS transistor NB2 are either completely on or completely off. Optionally, a swing transistor such as the NMOS swing transistor NA3 illustrated in FIG. 1, can be coupled between V.sub.CCB and PMOS latch transistor PB1 so as to perform the same function indicated for transistor NA3 of FIG. 1. The circuit illustrated in FIG. 2 provides translation without static current I.sub.CCt when V.sub.IN is logic-high, whether that logic-high is at a potential of 5 V or 3 V. The FIG. 2 circuit also provides translation without static current I.sub.CCt when V.sub.IN is logic-low, but only when V.sub.CCB &gt;V.sub.CCA. However, when V.sub.CCA &gt;V.sub.CCB and V.sub.IN is logic-low, I.sub.CCt does not equal zero because the potential at the gate of latch transistor PB1 is insufficient to turn that transistor off and a conduction path therefore exists from V.sub.CCA through blocking diode D1, transistors PA1 and PB1, to V.sub.CCB. Therefore, the translator is inadequate for all translation situations.
What is needed is a translation circuit that provides for transition from a subcircuit operating on a power supply at one potential to a subcircuit operating on a power supply at a different potential, and vice-versa. Further, what is needed is a translation circuit for translating a subcircuit operating on a 3 V supply to one operating on a 5 V supply, and vice-versa. Still further, what is needed is a 3 V,5 V translator that operates in all translation situations while maintaining I.sub.CCt essentially at zero.